The present invention relates to programmable logic circuits, and in particular, relates to the design of an improved field programmable logic device.
One type of high density programmable logic devices (xe2x80x9cPLDsxe2x80x9d) is the in-system programmable Large Scale Integration (ispLSI) family of devices from Lattice Semiconductor Corporation, Hillsboro, Oreg. An ispLSI device is reprogrammable in its application environment without being removed from the environment.
High density programmable logic devices, such as the ispLSI devices, are often referred to as xe2x80x9ccomplex PLDs.xe2x80x9d In a complex PLD, programmable logic functions are configured by programming a number of programmable logic blocks. Each programmable logic block typically includes a set of cells, in which each cell performs a single logic function and generates an output signal based on that logic function.
The number of logic functions that can be performed by a programmable logic device is typically limited by the number of cells in the device. Furthermore, the assignment of logic functions to the respective cells prior to programming the device can be a difficult task due to the limited availability of signal routing among cells within the programmable logic device. Generating an viable interconnect solution can be especially difficult when the number of logic functions to be performed is equal to or close to the number of cells, so that the programmable logic device is at or near capacity. Moreover, when the number of logic functions to be performed is greater than the number of cells in the device, the device is simply not capable of performing the desired functions.
Thus, a need has arisen for a programmable logic device that addresses the disadvantages and deficiencies of the prior art. In particular, the need has arisen for a programmable logic device with the capability to perform more than one logic function within each cell.
Accordingly, an improved programmable logic device is disclosed. In one embodiment, the programmable logic device includes a set of I/O cells, a set of logic blocks, and a routing pool that provides connections among the logic blocks and the I/O cells. At least one of the logic blocks includes a programmable logic array with a plurality of product term output lines. The programmable logic array generates a product term output signal on each product term output line. The logic block also includes a first product term summing circuit with a plurality of input terminals. At least one of the input terminals is coupled to at least one of the product term output lines. The first product term summing circuit generates an output signal at an output terminal in response to at least one product term output signal received at at least one respective input terminal. The logic block further includes a second product term summing circuit with a plurality of input terminals. At least one of the input terminals is coupled to at least one of the product term output lines. The second product term summing circuit generates an output signal at an output terminal in response to at least one product term output signal received at at least one respective input terminal. The logic block further includes first and second output lines and a first programmable switching device that programmably couples the first output line to the output terminal of a selected one of the first and second product term summing circuits. The logic block further includes a second programmable switching device that programmably couples the second output line to the output terminal of a selected one of the first and second product term summing circuits.
A technical advantage of the present invention is that each logic block is capable of performing two logic functions in each macrocell. Another technical advantage of the present invention is that generating an interconnect solution to program the programmable logic device is made simpler by the increased functional capacity of the device. Yet another technical advantage is that programmable output delays are provided to reduce output signal noise and increase the switching speed of time-critical output signals.